1. Field of the Invention
The present invention relates to semiconductor device fabrication and more specifically to a method and material for forming high density shallow trench isolation structures in integrated circuits, which are capable of withstanding wet etch treatments.
2. Description of the Related Art
In the semiconductor industry, there is a continuing trend toward higher device densities. In order to achieve integrated circuits (ICs) with increased performance, the characteristic dimensions of devices and spacings on the ICs continue to be decreased. To achieve these high densities there have been continuing efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features. It is also advantageous to reduce the scale of the isolation regions that are formed between the devices. Although the fabrication of smaller devices and isolation regions allows more devices to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects.
Fabrication of such devices often requires the deposition of dielectric materials into features patterned on substrates (such as Si, Ge, and other group III–V semiconductor substrates). In order to achieve proper isolation between devices in integrated circuits, a technique known as Shallow Trench Isolation (STI) is used. As the elements incorporated into a semiconductor device are integrated to a high degree, there is a growing tendency to increasingly use the STI method as a method of forming an isolation layer. STI involves forming trenches in a layer of silicon and then filling the trenches with silicon oxide. The trenches can be lined with a silicon oxide liner formed by a thermal oxidation process and then filled with additional silicon oxide or another material, such as polysilicon. These filled trenches define the size and placement of the active regions. The use of STI significantly shrinks the area needed to isolate transistors. Each isolated region is separated by the trenches and the insulating layer filled therein. In deep sub-micron integration, STI with higher aspect ratios (height/width) are required, which may have a width as small as 10 to 90 nm or even smaller in next generation devices. Aspect ratios may range from 10 to 60. Accordingly, there exists a need in the art for improved isolation between semiconductor devices and for techniques of fabricating improved isolation regions along with semiconductor devices. Clearly, there is a need to develop a material that can fill such narrow features without cracking and voids. Furthermore, the desired dielectric materials need to be able to withstand processing steps, such as high temperature anneal, chemical mechanical polishing (CMP), RIE etch, HF wet etch and cleaning steps.
In most cases, it is critical to have STI features completely filled with the dielectric materials without cracking and voids. Typically, dielectric materials are deposited by chemical vapor deposition (CVD) or by spin-on processes. The existing CVD (SACVD, LPCVD, HDP CVD and et. al.) and atomic layer deposition (ALD) approaches often lead to voiding inside of the trenches; and/or elaborative deposition/etch steps that are not feasible for gap-filling narrow features. In most cases it is important that the dielectric material completely fill such features, which may be as small as 0.01 to 0.05 μm or even smaller in next generation devices. Filling such narrow features, i.e. gap filling, places stringent requirements on materials used.
Several undesirable effects may arise from devices employing high aspect ratio STI. These include damage to the substrate due to excessive etching and severe microloading effects between dense and open trenches. Additionally, problems may result from incomplete clearing of etch by-product residue at the bottom of narrow trenches. Relatively narrow STI regions (e.g., about 180 {hacek over (A)} or less) formed using conventional techniques have a tendency lose their ability to isolate adjacent devices. The premetal dielectric (PMD) layer on an integrated circuit isolates structures electrically from metal interconnect layers and isolates them electrically from contaminant mobile ions that degrade electrical performance. PMD layers may require filling narrow gaps having aspect ratios, that is the ratio of depth to width, of five or greater. Accordingly, there exists a need in the art for improved isolation between semiconductor devices and for techniques of fabricating improved isolation regions along with semiconductor devices.
Spin-on glasses and spin-on polymers such as silicate, silazane, silisequioxane or siloxane generally exhibit good gap-fill properties. The silicon oxide films are formed by applying a silicon-containing pre-polymer onto a substrate followed by a bake and a high temperature anneal. Historically, the spin-on approach has been hampered by the unacceptable film cracking inside narrow trenches as the result of high film shrinkage after high temperature anneal which exceed 750° C. Film cracking can also lead to undesirable high HF wet etch rate and un-reliable yield issues. Thus, there exists a need in the art for dielectric spin-on materials that provides crack-free and void-free gap-fill of narrow features at high process temperatures. These materials need to have a very desirable degree of wet etch resistance and hardness which is comparable to PECVD oxide. The PMD materials also need to be able to withstand processing steps, such as etch, cleaning and chemical mechanical polishing steps. Thus there is a need for a PMD material that provides void-free gap-fill of narrow features and reasonable resistance to etching (both wet and dry etch) to survive subsequent processing steps. Such materials should also have adequate mechanical strength to withstand blank chemical mechanical polishing. The invention provides gap fill materials with such enhanced wet etch resistance. As density of a given material increases, its wet etch removal rate decreases. High density can be achieved by using a condensation/cross-linking catalyst including ammonium compounds, amines, phosphonium compounds and phosphine compounds. Through the use of a catalyst one can effectively lower the condensation temperature and/or drive the extent of cross-linking of silanol groups. Alternatively, one may enhance hydrophobicity of the materials so that its wetting property in an aqueous etching solution is diminished and hence, a greater resistance to aqueous wet etching solutions can be achieved. For example by increasing the organic content in the film through design of the materials. A balance between the amount of organic content, density of the film and mechanical strength has to be maintained. The material must withstand wet etch chemistries, i.e., diluted and buffered aqueous HF solutions.